The invention relates to a MOS transistor with low closing resistance, in particular for the voltage range from 20-30 V (medium voltage NMOS).
The presently used HV NMOS transistors with a cut-off voltage of up to approximately 150 volts are uneconomical in terms of surface area because of the voltage-optimized design for voltage ranges of about 20 volts. The diffused n-well used here as drain extension (FIG. 1), also in connection with a field plate (FIG. 2), represents the classical approach to increase the voltage sustaining capability. Since the doping of this n-well is configured in such a way that it is suitable to accept the complementary transistor (PMOS), its doping lies on a lower level. When the n-well is used as drain extension, it exerts a limiting effect on the performance of the transistor with regard to the current yield.
While the existing NMOS-logic transistor, on the other hand, is optimized in terms of the current yield, it does, not possess the necessary voltage sustaining capability.
In CMOS processes HV transistors for voltages of more than 30 volts may be realized in addition to the logic transistors for the 5-volt voltage range. These are optimized for peak voltages of 30/40/50 volts normally applied in the automotive range but also to promote suppression of interference pulses of up to approximately 150 volts. The voltage range from 10 volts to 30 volts, too, is at present covered by such HV transistors since special transistors do not exist. Higher performance and thus saving of surface area are to be achieved using specially optimized transistors for this voltage range.
An important boundary condition for design of the new MOS transistor is the CMOS process which is not to be modified or extended. The production of the new MOS transistor may not have any influence on the existing components and their parameters.
In conventional CMOS processes of up to approximately 1.0 xcexcm there are no possibilities of realising the new components without modifying the process and thus inducing modifications of the parameters of existing components. The reason for this phenomenon is the well design optimized in terms of high-voltage features since the logic transistors are produced in the high-voltage wells and there is thus no possibility of separately optimizing the logic and hiah-voltage portions.
In typical submicron technologies, i. e. mostly mixed technologies where logic and high-voltage components can be separately optimized, new wells are available besides the previously used well doping regions, which accept new complementary logic transistors with reduced gate oxide (so-called low-voltage transistors). These low-voltage wells are suitable for realization of the desired component.
An object of the invention is to create a MOS transistor having a low on-state resistance at high voltage sustaining capability and being producible by means of the process steps for logic MOS transistors.
To solve this object the present invention suggests a MOS transistor with high voltage sustaining capability and low closing resistance, which comprises
a substrate doped with charge carriers of a first line type,
drain and source regions configured in the substrate, which are doped with charge carriers of a second line type opposed to the first line type,
a gate electrode arranged in the region between the drain and the source region on the substrate and comprising a drain-side end region,
a drain extension region doped with charge carriers of the second line type, connected with the drain region and extending to below the drain-side end of the gate electrode.
This MOS transistor according to the present invention is characterized in that
the drain extension region is produced by an ion implantation process comprising at least one first implantation step, and
the drain extension region comprises in its region located near the top side and facing the top side of the substrate a lower doping material concentration than in its region below the region located near the top side.
In the MOS transistor according to the invention the drain extension region required to increase the voltage sustaining capability is produced by an ion implantation step with the implantation comprising a lower doping material concentration in its region located near the top side and facing the top side of the substrate than in its region below the region located near the top side. In other words, the drain extension region comprises a so-called retrograde profile. This offers the advantage that an implanted retrograde well can be a drain extension as is used for low-voltage transistors (logic transistors) in typical submicron technologies. Thus process steps can be applied for the production of the MOS transistor according to the present invention, which are presently applied to the production of integrated low-voltage MOS logic transistors. The process control thus remains unchanged and, what is of particular importance, is not extended by additional process steps. The thermal balance also remains unchanged.
In a preferred embodiment of the present invention it is further envisaged to realize the drain extension region by means of a two or three-step implantation process with the ion implantations applied to low-voltage transistors being used as second and/or third implantations for threshold value adjustment and prevention of a punch through effect.
Another advantage of the MOS transistor according to the present invention is the achievement of an increased performance with reduced surface area requirement. The current yield of the HV transistor according to the present invention is improved whereas the voltage sustaining capability is limited to a certain extent due to the less smooth doping patterns in the corner regions of the retrograde implantation profile. However, the voltage sustaining capability is sufficient to meet the requirements applicable to automotive application so that for the transistor according to the present invention above all the surface area saving proves an asset.
The essential innovation presented by the MOS transistor according to the present invention thus is the use of a retrograde well profile to produce a drain extension so that retrograde wells optimized for the low-voltage logic transistors can be used as drain extension for high-voltage components, which results in both an unchanged and simple process control without additional steps.
Contrary to the classical process for production of a diffused drain extension to improve the voltage sustaining capability an implanted retrograde doping profile is used according to the present invention. This profile comprises 1 to 3 implantations depending on the process control applied:
the well implantation (WI) proper, high-energy implanted at a large depth of  greater than 1 xcexcm,
possibly the VT implantation (VTI) near the surface to adjust the closing threshold (threshold value adjustment) and/or
possibly an anti-punch through implantation (APTI) approximately at the depth or the drain/source regions ( less than 0.5 xcexcm) which limits the expansion of the space charge region on the drain towards the source.
The implantations (WI and APTI) are masked by the field oxide and thus only reach the active regions. The WI penetrates the field oxide and forms a high-doped layer immediately thereunder in depth direction. Combination of both in a component with field plate as is envisaged according to a preferred embodiment of the present invention results in the following advantages/disadvantages as compared with the classical process:
In the active region below the gate particularly the APTI prevents an increased field at the field oxide fringe since it decreases the doping gradient of the drain well. This improves the voltage sustaining capability.
In the region below the field plate, the WI produces a low-ohm connection of the drain to the channel. This has a positive effect on the current yield of the transistor and represents the essential improvement as compared with the classical process.
The less smooth doping patterns in the corners of the retrograde implantation profile limit the voltage sustaining capability achievable at maximum. It thus typically lies below the values achievable by means of the classical method:
Further, when using the implantation profile described above, a component without field plate could possibly be employed. When using this component a smaller surface area is required at reduced voltage sustaining capability with the same advantages being made use of.
Another increase in the voltage sustaining capability is feasible with a so-called xe2x80x9cmodulated well implantationxe2x80x9d (PCT application PCT/EP96/04246, publication no. WO-A-97/13277). This method is also applicable to She components described above which is the reason why the contents of the PCT application has been made the subject matter of the present application.
It must be said here that the new components described herein cannot only be realized as n-channel transistor. A p-channel transistor is also feasible by using the p-low-voltage well as drain extension inside the existing HV-n-well as body.